It is customary in the manufacture of integrated circuits, to form dielectric layers between conductors which interconnect various portions of the circuit. The conductive interconnections, known as "runners," may be made from a metal, such as aluminum or tungsten, or may be made from doped poly-silicon, perhaps with an overlaying layer of silicide. In some applications, the entire runner may be made from silicide.
It is sometimes desired, for example, in certain SRAM applications, to have a comparatively thin dielectric layer between the second- and the third-level conductors. One method for providing such an inter-level dielectric is to use low-pressure chemical vapor deposition (LPCVD) of silicon dioxide from an appropriate precursor gas, such as TEOS. However, the relatively high (approximately 720.degree. C.) deposition temperature of LPCVD TEOS may cause degradation of silicided runners.
Plasma-enhanced TEOS processes (PETEOS) utilize a lower deposition temperature (approximately 390.degree. C.), but are often too fast (i.e., deposit material too quickly) and produce material layers of uneven quality. Typical standard PETEOS processes can produce a comparatively thick (10,000 .ANG.) dielectric film at a rate of approximately 125 .ANG. per second. However, this deposition rate is too fast for situations in which a thin (approximately 1000 .ANG.) or ultra-thin (approximately 100 .ANG.) dielectric is desired because the deposition process is not completely stable in the first few seconds after startup.